Recently, with the advances in semiconductor fabrication techniques, a trend has proceeded toward smaller design rules for semiconductor devices, e.g., 1 Gbit dynamic random access memories (DRAMs), to the extent that an alignment margin can hardly be secured when aligning a contact plug with a semiconductor layer or interconnect layer underlying the contact plug. Accordingly, for sub-quarter micron semiconductor devices, a manufacturing process is employed which permits the contact plug to be formed by self-alignment with a semiconductor layer or an interconnect layer underlying the contact plug.
The advantages of using a self-aligned contact (SAC) are that a misalignment margin can be increased during a required photolithography process and that a contact resistance can be reduced. For these reasons, emphasis has recently been place upon SAC techniques.
However, as the pattern size of semiconductor devices decreases, there is an increased possibility of a short circuit between a contact hole and a gate line. Contact holes of a high integration density device such as in a memory device inevitably require a high aspect ratio, that is, a smaller surface area comparing with their depth. Therefore, an etch stop phenomenon may occur during the formation of the contact holes. Also, it becomes very difficult to deposit the interlayer insulating film over the fine pattern structure having a high aspect ratio without creating voids and discontinuities in the insulating material.
To solve problems mentioned above, a method has been proposed that uses a contact pad. A conventional method for forming contact hole using an SAC pad will be described below with reference to the FIG. 1 and FIGS. 2A to 2C.
FIG. 1 is a top plan view showing an SAC contact structure according to a conventional semiconductor manufacturing method, and FIG. 2A to FIG. 2C are cross-sectional views of the conventional method for forming the SAC contact pad, which are taken along the line II-II' line of FIG. 1.
Referring to FIG. 2A, a device isolation region 12 is formed over a semiconductor substrate 10 to define active and inactive regions. The device isolation region 12 may be formed by any suitable method well known in the art, for example, shallow trench isolation (STI) or the local oxidation of silicon (LOCOS).
Though not shown, a gate oxide layer is formed by conventional method, e.g., a thermal oxidation method over the entire surface of the substrate. A gate electrode conductive layer and a gate capping insulating layer are laminated over the gate oxide layer in that order. The gate electrode conductive layer is generally laminated with a polysilicon layer 14 and a tungsten silicide layer 16 (first and second gate electrodes), and the gate capping insulating layer is laminated with a first silicon nitride layer 18 and second silicon nitride layer 20 (first and second gate capping layers). In some cases, the second silicon nitride layer 20 can be replaced with a silicon oxide layer. The gate capping layer generally has an etching selectivity with respect to a subsequent interlayer insulating film 26.
Next, a conventional photolithography process is conducted on the gate electrode conductive layer and the gate capping insulating layer to form gate electrode structure 21, i.e., the combination of the first and second gate capping layers 18 and 20 and the first and second gate electrodes 14 and 16.
A low concentration impurity ions are then implanted into the active region of the semiconductor substrate 10 outside of the gate electrode structure 21. A gate spacer 22 is formed to coat the gate electrode structure 21, and this gate spacer 22 has an etching selectivity with respect to a subsequent interlayer insulating film 26. The gate spacer is generally formed of silicon nitride (SiN). Thereafter, high concentration impurity ions are implanted into the active region of the semiconductor substrate 10 outside of the gate spacer 22 in the peripheral region of the semiconductor substrate.
An etch stop layer 24 is formed over the semiconductor substrate 10 and serves as an etching stopper during the step of an SAC etching process. The etch stop layer 24 also has an etching selectivity with respect to the subsequent interlayer insulating film 26, and is formed of, for example, silicon nitride or silicon oxynitride. After the formation of the etch stop layer 24, an interlayer insulating film 26 is deposited over the semiconductor substrate 10 and the gate electrode structures 21.
Referring to FIG. 2B, a photoresist pattern (not shown) is deposited over the interlayer insulating film 26. The interlayer insulating film 26 and the etch stop layer 24 are etched away using the photoresist pattern as a mask to form openings 28a and 28b.
Referring to FIG. 2C, the photoresist pattern is then removed and the openings 28a and 28b are filled with conductive material such as a polysilicon layer. The polysilicon layer is then planarized by a process such as chemical mechanical polishing (CMP) process or an etch-back process to thereby form contact pads, i.e., bit line contact pads 30b and storage node contact pads 30a.
However, in such a conventional method for forming an SAC contact pad, the self aligned contact pattern, i.e., the photoresist pattern, is a circular or elliptical type, as shown in FIG. 1. Therefore as the device pattern size becomes smaller, i.e., as the aspect ratio of the contact hole becomes high, the area to be etched reduces and the depth of the contact hole increases. As a result, during the etching of the interlayer insulating film, the etching rate becomes smaller, in the most severe case, the reaction byproduct cannot diffuse out of the contact hole. In this case, the etching rate can be significantly reduced or etching can cease altogether, i.e., an etch-stop phenomenon can occur.
To solve the etch-stop phenomenon, the etching must be performed under conditions such that the formation of byproduct such as a polymer is suppressed and the etching time is increased. However, in the case of such an etching recipe, the gate capping layer and the gate spacer are also etched during the etching step, thereby resulting in short circuit between the SAC pad and gate.
Y.Kohyama et al, have proposed a method for forming an SAC contact pad that uses a contact pattern merging storage node contact hole and bit line contact hole in an article entitled "A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond," symposium on VLSI tech, Digest of Technical Papers, pp. 17-18, 1997.
In this proposed method, a gate SAC pattern (which indicates a resist area) is the same as an active area, and is shifted by a half pitch in the gate direction. Therefore, the photoresist pattern area is so small that the polymer formation is very low during the formation of the contact hole. As a result, the etching selectivity between the interlayer insulating film and the nitride layer of gate spacer and gate mask layer becomes poor. This is because the polymer formation is proportional to the photoresist pattern area and the etching selectivity ratio increases with polymer formation.
Furthermore, the SAC contact pad has an upper limit in size between the pair of gate lines. In other words, the contact pads 30a and 30b are formed between the pair of gates 23 as shown in FIG. 1. Therefore, there is still possibility of misalignment between the SAC contact pad and the storage node or bit line.